Semiconductor Design Automation Consulting
CAD support, PDK support, rule deck support and PD support — the design infrastructure layer, run by engineers who have owned in-house PDKs, certified models and qualified tools inside foundries, EDA vendors and fabless design houses.
Four support lines across the design infrastructure layer — the environment your designers work in, the kit they design with, the decks that sign them off, and the implementation that closes the block.
Design environment enablement end to end — launchers and utilities in SKILL and Tcl, EDA tool qualification and benchmarking, regression harnesses, and Linux CAD deployment, so your designers start work instead of debugging the flow.
Discuss this servicePDK development, maintenance and validation on Cadence and Synopsys — techfiles, CDF and callbacks, PCELL generation, physical verification decks, RC extraction flows, P&R techfiles, and advanced package enablement for 3DIC and CoWoS.
Discuss this serviceDRC deck projects run with leading foundries — runset development and qualification against QA cells and real designs, detailed requirement documents carried through with R&D to closure, and tutorial material that trains your team on the flow.
Discuss this serviceComplete netlist-to-GDS physical design at advanced nodes on multi-voltage, multi-corner and low-power blocks — floorplan, APR, timing closure, IR/EM analysis, layout verification and tape-out, handled end to end rather than handed back.
Discuss this serviceReach out to discuss your project — scoping, engagement models, and technical questions on any of the four support lines.